A flash memory is a non-volatile semiconductor storage device for accumulating information in a floating gate electrode, in the form of electric charges. A flash memory has a simple configuration, and is thus appropriately used for configuring a large-scale integrated circuit device.
A typical flash memory is formed as follows. On a silicon substrate, a floating gate electrode made of polysilicon is formed via a tunnel insulating film made of a thermally-oxidized film or the like. A stacked gate structure formed by laminating control gate electrodes, is formed on the floating gate electrode via an interlayer insulating film. In the silicon substrate, a source area and a drain area are formed on a first side of the stacked gate structure and a second side of the stacked gate structure, respectively.
Patent document 1: Japanese Laid-Open Patent Publication No. 2006-128164
Patent document 2: U.S. Pat. No. 6,635,916
Patent document 3: U.S. Pat. No. 5,583,359
Patent document 4: U.S. Pat. No. 7,348,624
Patent document 5: U.S. Pat. No. 5,208,725
Patent document 6: U.S. Pat. No. 6,737,698
Patent document 7: U.S. Pat. No. 5,978,206
Meanwhile, recently, there is demand for a semiconductor integrated circuit device in which such a non-volatile semiconductor device is integrated on a common semiconductor substrate together with an analog device having an analog capacitor, and a logical device.
In such a semiconductor integrated circuit device in which an analog device is integrated, if an analog capacitor in which a lower electrode pattern and an upper electrode pattern are facing each other in a vertical direction is formed via an interlayer insulating film, it may be difficult to attain sufficient capacitance.
Therefore, in the conventional technology, there has been proposed a semiconductor integrated circuit device in which wiring patterns formed in a multilayer wiring structure are used for forming a comb-tooth type analog capacitor.
However, recently, an ultra-miniaturized semiconductor device including such a comb-tooth type capacitor formed in a multilayer wiring structure is demanded to have even higher capacitance, in accordance with the miniaturization of patterns.